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Disambiguation of "Katsurai, Hiroaki"

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A 25G Burst-mode Receiver with -27.7-dBm Sensitivity and 150-ns Response-Time for 50G-EPON Systems.

, , , , , , , and . ECOC, page 1-3. IEEE, (2020)

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Hiroaki Kobayashi

Hiroaki Tanaka

 

Other publications of authors with the same name

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC., , , , , and . ISSCC, page 226-227. IEEE, (2008)High-power SOA integrated EADFB laser and high-sensitivity burst-mode APD receiver toward 10G- and 25G-class long reach PON., , , , , , , , and . OECC/PSC, page 1-3. IEEE, (2022)A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS., , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2018)20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters., , , , and . ISCAS, page 2696-2699. IEEE, (2014)A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1288-1295 (2015)A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops., , , , , , and . ISCAS, page 2704-2707. IEEE, (2014)Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit., , , , , and . ISSCC, page 104-105. IEEE, (2009)A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si., , , , , , , , , and 5 other author(s). OFC, page 1-3. IEEE, (2018)A 25G Burst-mode Receiver with -27.7-dBm Sensitivity and 150-ns Response-Time for 50G-EPON Systems., , , , , , , and . ECOC, page 1-3. IEEE, (2020)