Author of the publication

A processor element for a mixed signal cellular processor array vision chip.

, , and . ISCAS, page 1564-1567. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Live demonstration: Real-time image processing on ASPA2 vision system., , , and . ISCAS, page 1989. IEEE, (2011)A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology., , and . ECCTD, page 193-196. IEEE, (2009)A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array., and . CICC, page 1-4. IEEE, (2013)Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing., and . ISCAS, IEEE, (2006)Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision., , , , and . ISCAS, page 447. IEEE, (2014)Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array., and . ECCTD, page 84-87. IEEE, (2007)ASPA: Focal Plane digital processor array with asynchronous processing capabilities., and . ISCAS, page 1592-1595. IEEE, (2008)A processor element for a mixed signal cellular processor array vision chip., , and . ISCAS, page 1564-1567. IEEE, (2011)Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps., , , , and . ICECS, page 324-327. IEEE, (2012)Architecture and design of a programmable 3D-integrated cellular processor array for image processing., and . VLSI-SoC, page 349-353. IEEE, (2011)