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Disambiguation of "Yamazaki, Koji"

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Post-BIST Fault Diagnosis for Multiple Faults.

, , , , , , and . IEICE Trans. Inf. Syst., 91-D (3): 771-775 (2008)

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Koji Kameo

Satoko Yamazaki

Koji Onoda

Koji Ota

Tomoko Kojima

 

Other publications of authors with the same name

Accelerating SDN/NFV with Transparent Offloading Architecture., , , , and . ONS, USENIX Association, (2014)Attempts Toward Behavior Recognition of the Asian Black Bears Using an Accelerometer., , , , and . ABC, volume 291 of Smart Innovation, Systems and Technologies, page 57-79. Springer, (2021)A simple technique for locating gate-level faults in combinational circuits., , and . Asian Test Symposium, page 65-70. IEEE Computer Society, (1995)A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model., , , and . PRDC, page 217-218. IEEE Computer Society, (2017)A heuristic algorithm for reducing system-level test vectors with high branch coverage., , , , and . ISCAS, page 1475-1478. IEEE, (2011)Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture., , and . IEICE Trans. Commun., 103-B (1): 11-19 (2020)Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines., , , , , , , , and . ATS, page 39-44. IEEE, (2007)A Novel Approach for Improving the Quality of Open Fault Diagnosis., , , , , , , and . VLSI Design, page 85-90. IEEE Computer Society, (2009)Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC., , , , , , , and . VLSI Design, page 91-96. IEEE Computer Society, (2009)An approach to diagnose logical faults in partially observable sequential circuits., and . Asian Test Symposium, page 168-173. IEEE Computer Society, (1997)