( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A Novel Approach for Improving the Quality of Open Fault Diagnosis.

, , , , , , , и . VLSI Design, стр. 85-90. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Keiko Hashizume

Masaki Nakajima

 

Другие публикации лиц с тем же именем

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , и . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , и . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , и . Asian Test Symposium, стр. 423-428. IEEE Computer Society, (2002)Reducing Scan Shifts Using Folding Scan Trees., , , , и . Asian Test Symposium, стр. 6-11. IEEE Computer Society, (2003)Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code., , и . Asian Test Symposium, стр. 163-166. IEEE Computer Society, (2010)New Class of Tests for Open Faults with Considering Adjacent Lines., , , , , , и . Asian Test Symposium, стр. 301-306. IEEE Computer Society, (2009)Identification of Feedback Bridging Faults with Oscillation., , и . Asian Test Symposium, стр. 25-. IEEE Computer Society, (1999)Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2014)A built-in test circuit for open defects at interconnects between dies in 3D ICs., , , , и . 3DIC, стр. 1-5. IEEE, (2011)Fault Detection of Combinational Circuits Based on Supply Current., , , и . ITC, стр. 374-380. IEEE Computer Society, (1988)