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Disambiguation of "Vianello, Elisa"

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Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.

, , , , , , , , and . AICAS, page 136-140. IEEE, (2020)

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Alessandro Vianello

Mirko Vianello

Stephan Elisat

Ahmad Elisa

Willy Elisat

 

Other publications of authors with the same name

Insect-Inspired Elementary Motion Detection Embracing Resistive Memory and Spiking Neural Networks., , , , , , and . Living Machines, volume 10928 of Lecture Notes in Computer Science, page 115-128. Springer, (2018)2021 Roadmap on Neuromorphic Computing and Engineering., , , , , , , , , and 46 other author(s). CoRR, (2021)Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors., , , , , , , , , and . DATE, page 1-2. IEEE, (2023)A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array., , , , , , and . ISCAS, page 2440-2443. IEEE, (2013)Stochastic neuron design using conductive bridge RAM., , , , and . NANOARCH, page 95-100. IEEE Computer Society, (2013)OxRAM-based non volatile flip-flop in 28nm FDSOI., , , , , and . NEWCAS, page 141-144. IEEE, (2014)Resistive memories: Which applications?, , , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)The Logarithmic Memristor-Based Bayesian Machine., , , , , , , , , and 2 other author(s). CoRR, (2024)Characterization and modelling of silicon-nitride based non volatile memories.. University of Udine, Italy, (2010)1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing., , , , , , , , , and 10 other author(s). IMW, page 1-4. IEEE, (2022)