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Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.

A. Laborieux, M. Bocquet, T. Hirtzlin, J. Klein, L. Diez, E. Nowak, E. Vianello, J. Portal, and D. Querlioz. AICAS, page 136-140. IEEE, (2020)

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Jacques Klein

Jacques-Olivier Lachaud

Jerome Olivier Klein

Jacques Neumann

Jacques Minlo

Other publications of authors with the same name

Synthesis of Finite State Machines with Magnetic Domain Wall Logic.J. Klein, E. Belhaire, C. Chappert, F. Ouchet, R. Cowburn, D. Read, and D. Petit. ISCAS, page 133-136. IEEE, (2007)Spin-electronics based logic fabrics.W. Zhao, J. Klein, Z. Wang, Y. Zhang, N. Romdhane, D. Querlioz, D. Ravelosona, and C. Chappert. VLSI-SoC, page 174-179. IEEE, (2013)Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.Y. Zhang, C. Zhang, J. Klein, D. Ravelosona, G. Sun, and W. Zhao. ISCAS, page 381-384. IEEE, (2015)Synchronous full-adder based on complementary resistive switching memory cells.Y. Zhang, E. Deng, J. Klein, D. Querlioz, D. Ravelosona, C. Chappert, W. Zhao, M. Moreau, J. Portal, M. Bocquet and 3 other author(s). NEWCAS, page 1-4. IEEE, (2013)Embedded MRAM for high-speed computing.W. Zhao, Y. Zhang, Y. Lakys, J. Klein, D. Etiemble, D. Revelosona, C. Chappert, L. Torres, L. Cargnini, R. Brum and 2 other author(s). VLSI-SoC, page 37-42. IEEE, (2011)Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.T. Hirtzlin, B. Penkovsky, J. Klein, N. Locatelli, A. Vincent, M. Bocquet, J. Portal, and D. Querlioz. NANOARCH, page 1-5. IEEE, (2019)Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.Y. Wang, Y. Zhang, E. Deng, J. Klein, L. Naviner, and W. Zhao. Microelectron. Reliab., 54 (9-10): 1774-1778 (2014)Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.N. Romdhane, W. Zhao, Y. Zhang, J. Klein, Z. Wang, and D. Ravelosona. NANOARCH, page 71-76. IEEE Computer Society/ACM, (2014)Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.D. Zhang, L. Zeng, Y. Zhang, W. Zhao, and J. Klein. NANOARCH, page 173-178. ACM, (2016)High Performance SoC Design Using Magnetic Logic and Memory.W. Zhao, L. Torres, L. Cargnini, R. Brum, Y. Zhang, Y. Guillemenet, G. Sassatelli, Y. Lakys, J. Klein, D. Etiemble and 2 other author(s). VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 10-33. Springer, (2011)

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Disambiguation of "Klein, Jacques-Olivier"

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Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.

Please choose a person to relate this publication to

Jacques Klein

Jacques-Olivier Lachaud

Jerome Olivier Klein

Jacques Neumann

Jacques Minlo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Klein, Jacques-Olivier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.

Please choose a person to relate this publication to

Jacques Klein

Jacques-Olivier Lachaud

Jerome Olivier Klein

Jacques Neumann

Jacques Minlo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.