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HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , и 14 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2021)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , и . ISSCC, стр. 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , и . ISSCC, стр. 358-360. IEEE, (2018)A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS., , , , , , , , , и . ISSCC, стр. 468-469. IEEE, (2013)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 266-268. IEEE, (2018)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , и 1 other автор(ы). A-SSCC, стр. 89-92. IEEE, (2014)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , и 2 other автор(ы). ESSCIRC, стр. 183-186. IEEE, (2017)22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , и . ISSCC, стр. 378-379. IEEE, (2014)