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Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology., , , , , , , и . ESSCIRC, стр. 67-70. IEEE, (2021)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , и . ISSCC, стр. 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , и . ISSCC, стр. 358-360. IEEE, (2018)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS., , , , , и . IEEE J. Solid State Circuits, 44 (11): 2901-2910 (2009)A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement., , , , , , и . ISSCC, стр. 2082-2091. IEEE, (2006)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , и 6 other автор(ы). A-SSCC, стр. 239-240. IEEE, (2019)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , и 3 other автор(ы). ISCAS, стр. 1-5. IEEE, (2018)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , и 1 other автор(ы). ESSCIRC, стр. 115-118. IEEE, (2017)