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Disambiguation of "Kull, Lukas"

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22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS.

, , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)

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Melanie Kull

Produktion des staphylolytischen Enzyms Lysostaphin in Staphylokokken und Charakterisierung einer femB-Deletionsmutante in Staphylococcus carnosus TM300. Uni Tübingen, (2009)

Edgar Kull

Wilhelmine Kull

Wiebke Kull

Stephan Kull

 

Other publications of authors with the same name

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)Measurement of high-speed ADCs., and . CICC, page 1-7. IEEE, (2017)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , and 6 other author(s). A-SSCC, page 239-240. IEEE, (2019)Challenges in implementing high-speed, low-power ADCs in CMOS.. OFC, page 1-3. IEEE, (2015)A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS., , , , , , , , , and 1 other author(s). A-SSCC, page 89-92. IEEE, (2014)