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Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops., , , , и . J. Circuits Syst. Comput., 24 (10): 1550153:1-1550153:17 (2015)DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems., , и . CoRR, (2023)A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks., , , и . CoRR, (2022)Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices., , и . ISQED, стр. 49-54. IEEE, (2018)Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing., , , и . IET Circuits Devices Syst., 11 (3): 274-279 (2017)SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures., , , , , и . DAC, стр. 1-6. IEEE, (2020)Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network., и . HOST, стр. 89-92. IEEE, (2022)Enabling Efficient Training of Convolutional Neural Networks for Histopathology Images., , и . ICIAP Workshops (1), том 13373 из Lecture Notes in Computer Science, стр. 533-544. Springer, (2022)Deep Mapper: A Multi-Channel Single-Cycle Near-Sensor DNN Accelerator., , , , , , и . ICRC, стр. 1-5. IEEE, (2023)Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (7): 678-682 (2016)