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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou, Z. Zhang, S. Sie, W. Wei, Y. Lo, T. Wen, T. Hsu, Y. Chen, W. Shih, C. Lo, R. Liu, C. Hsieh, K. Tang, N. Lien, W. Shih, Y. He, Q. Li, and M. Chang. ISSCC, page 246-248. IEEE, (2020)

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Angelika Ning

Jing Ning

Hans Ningel

Werner Yu-fung Ning

Michael Ningler

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Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.S. Srinivasa, W. Chen, Y. Tu, M. Chang, J. Sampson, and V. Narayanan. ISCAS, page 1-5. IEEE, (2019)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.X. Si, J. Chen, Y. Tu, W. Huang, J. Wang, Y. Chiu, W. Wei, S. Wu, X. Sun, R. Liu and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.Y. Chiu, Z. Zhang, J. Chen, X. Si, R. Liu, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang and 3 other author(s). ISSCC, page 138-140. IEEE, (2019)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)

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Disambiguation of "Tu, Yung-Ning"

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

Please choose a person to relate this publication to

Angelika Ning

Jing Ning

Hans Ningel

Werner Yu-fung Ning

Michael Ningler

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tu, Yung-Ning"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

Please choose a person to relate this publication to

Angelika Ning

Jing Ning

Hans Ningel

Werner Yu-fung Ning

Michael Ningler

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.