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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang, Z. Zhang, H. Jiang, S. Huang, C. Lo, R. Liu, C. Hsieh, K. Tang, S. Sheu, S. Li, H. Lee, S. Chang, S. Yu, and M. Chang. ISSCC, page 240-242. IEEE, (2020)

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Jing Wang

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A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.Y. Chiu, Z. Zhang, J. Chen, X. Si, R. Liu, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)Leveraging High-Order Similar Nodes and Structural Correlation for Attention-Based Graph Embedding.J. Wang, C. Li, and J. Yang. ICMLC, page 248-259. IEEE, (2023)On intrusion detection matching algorithm from the perspective of multi- agent.J. Wang, Y. Dong, and H. Liu. ICMLC, page 601-606. IEEE, (2012)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.C. Xue, W. Chen, J. Liu, J. Li, W. Lin, W. Lin, J. Wang, W. Wei, T. Chang, T. Chang and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.X. Si, J. Chen, Y. Tu, W. Huang, J. Wang, Y. Chiu, W. Wei, S. Wu, X. Sun, R. Liu and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)Double Distillation of BERT Combined with GCN for Text Classification.J. Wang, J. Zhao, and C. Feng. ICMLC, page 284-294. IEEE, (2023)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.C. Xue, T. Huang, J. Liu, T. Chang, H. Kao, J. Wang, T. Liu, S. Wei, S. Huang, W. Wei and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)Qualitative simulation of the panic spread in large-scale evacuation.J. Wang, S. Lo, J. Sun, Q. Wang, and H. Mu. Simul., 88 (12): 1465-1474 (2012)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)

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Disambiguation of "Wang, Jing-Hong"

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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

Please choose a person to relate this publication to

Jing Wang

Jing Wang

Jing Wang

Jing Wang

Jing Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Jing-Hong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

Please choose a person to relate this publication to

Jing Wang

Jing Wang

Jing Wang

Jing Wang

Jing Wang

Other publications of authors with the same name

Disambiguation

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URL
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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.