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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang, Z. Zhang, H. Jiang, S. Huang, C. Lo, R. Liu, C. Hsieh, K. Tang, S. Sheu, S. Li, H. Lee, S. Chang, S. Yu, and M. Chang. ISSCC, page 240-242. IEEE, (2020)

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Pei-Jung Chiang

Pei-Jung Chen

Pei-Jung Chung

Lu Lu

Pei Li

Other publications of authors with the same name

Complementary QA network analysis for QA retrieval in social question-answering websites.D. Liu, Y. Chen, M. Shen, and P. Lu. J. Assoc. Inf. Sci. Technol., 66 (1): 99-116 (2015)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.J. Su, P. Lu, P. Wu, Y. Chou, T. Liu, Y. Chung, L. Hung, J. Ren, W. Huang, C. Chien and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)DAH: Domain Adapted Deep Image Hashing.P. Lu, P. Ma, Y. Chang, and M. Yeh. ISPACS, page 1-2. IEEE, (2021)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)

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Disambiguation of "Lu, Pei-Jung"

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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

Please choose a person to relate this publication to

Pei-Jung Chiang

Pei-Jung Chen

Pei-Jung Chung

Lu Lu

Pei Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lu, Pei-Jung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.

Please choose a person to relate this publication to

Pei-Jung Chiang

Pei-Jung Chen

Pei-Jung Chung

Lu Lu

Pei Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.