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Synchronous full-adder based on complementary resistive switching memory cells.

Y. Zhang, E. Deng, J. Klein, D. Querlioz, D. Ravelosona, C. Chappert, W. Zhao, M. Moreau, J. Portal, M. Bocquet, H. Aziza, D. Deleruyelle, and C. Muller. NEWCAS, page 1-4. IEEE, (2013)

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Cynthia Moreau

Patrick Moreau

Dorothee Moreau

Erwan Moreau

Dirk Moreau

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Multilevel operation in oxide based resistive RAM with SET voltage modulation.H. Aziza, H. Ayari, S. Onkaraiah, M. Moreau, J. Portal, and M. Bocquet. DTIS, page 1-5. IEEE, (2016)A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks.H. Aziza, M. Moreau, A. Pérez, A. Virazel, and P. Girard. NEWCAS, page 1-4. IEEE, (2019)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.W. Zhao, J. Portal, W. Kang, M. Moreau, Y. Zhang, H. Aziza, J. Klein, Z. Wang, D. Querlioz, D. Deleruyelle and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures.A. Levisse, B. Giraud, J. Noël, M. Moreau, and J. Portal. NVMTS, page 1-4. IEEE, (2015)Design of Hybrid CMOS Non-Volatile SRAM Cells in 130nm RRAM Technology.H. Bazzi, A. Harb, H. Aziza, and M. Moreau. ICM, page 228-231. IEEE, (2018)Storage Class Memory with Computing Row Buffer: A Design Space Exploration.V. Egloff, J. Noel, M. Kooli, B. Giraud, L. Ciampolini, R. Gauchi, C. Tortolero, E. Guthmuller, M. Moreau, and J. Portal. DATE, page 1-6. IEEE, (2021)An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits.H. Aziza, H. Bazzi, J. Postel-Pellerin, P. Canet, M. Moreau, and A. Harb. DTIS, page 1-5. IEEE, (2019)Comparison between Lagrangian and mesoscopic Eulerian modelling approaches for inertial particles suspended in decaying isotropic turbulence.A. Kaufmann, M. Moreau, O. Simonin, and J. Hélie. J. Comput. Phys., 227 (13): 6448-6472 (2008)Single-ended sense amplifier robustness evaluation for OxRRAM technology.H. Aziza, M. Bocquet, M. Moreau, and J. Portal. IDT, page 1-5. IEEE, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.A. Levisse, B. Giraud, J. Noel, M. Moreau, and J. Portal. NANOARCH, page 7-12. ACM, (2016)

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Disambiguation of "Moreau, Mathieu"

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Synchronous full-adder based on complementary resistive switching memory cells.

Please choose a person to relate this publication to

Cynthia Moreau

Patrick Moreau

Dorothee Moreau

Erwan Moreau

Dirk Moreau

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Moreau, Mathieu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Synchronous full-adder based on complementary resistive switching memory cells.

Please choose a person to relate this publication to

Cynthia Moreau

Patrick Moreau

Dorothee Moreau

Erwan Moreau

Dirk Moreau

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Synchronous full-adder based on complementary resistive switching memory cells.