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Tiered-latency DRAM: A low latency and low cost DRAM architecture.

, , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)

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Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems., , , , and . CoRR, (2018)Linearly compressed pages: a low-complexity, low-latency main memory compression framework., , , , , , , and . MICRO, page 172-184. ACM, (2013)Half-Double: Hammering From the Next Row Over., , , , , , , , and . USENIX Security Symposium, page 3807-3824. USENIX Association, (2022)S-COI : The Secure Conflicts of Interest Model for Multilevel Secure Database Systems., , and . DASFAA, volume 2973 of Lecture Notes in Computer Science, page 146-153. Springer, (2004)RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization., , , , , , , , , and 1 other author(s). MICRO, page 185-197. ACM, (2013)Improving DRAM performance by parallelizing refreshes with accesses., , , , , , and . HPCA, page 356-367. IEEE Computer Society, (2014)An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms., , , , and . ISCA, page 60-71. ACM, (2013)Tiered-latency DRAM: A low latency and low cost DRAM architecture., , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)A case for exploiting subarray-level parallelism (SALP) in DRAM., , , , and . ISCA, page 368-379. IEEE Computer Society, (2012)Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior., , , and . MICRO, page 65-76. IEEE Computer Society, (2010)