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Tiered-latency DRAM: A low latency and low cost DRAM architecture.

, , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)

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GrandSLAm: Guaranteeing SLAs for Jobs in Microservices Execution Frameworks., , , , , and . EuroSys, page 34:1-34:16. ACM, (2019)BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3071-3087 (2016)DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators., , , and . ACM Trans. Archit. Code Optim., 12 (4): 65:1-65:28 (2016)MISE: Providing performance predictability and improving fairness in shared main memory systems., , , , and . HPCA, page 639-650. IEEE Computer Society, (2013)Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping., , , , , and . ASPLOS (3), page 900-915. ACM, (2024)Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms., , , , , , , and . SIGMETRICS (Abstracts), page 54. ACM, (2017)Tackling memory access latency through DRAM row management., , , , and . MEMSYS, page 137-147. ACM, (2018)A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters., , , , , and . VEE, page 93-106. ACM, (2015)Tiered-latency DRAM: A low latency and low cost DRAM architecture., , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)