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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator., , , , и . A-SSCC, стр. 201-204. IEEE, (2017)A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure., , , , , и . CICC, стр. 1-4. IEEE, (2013)Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis., , и . ISQED, стр. 572-579. IEEE, (2012)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , и . ISCAS (1), стр. 73-76. IEEE, (2005)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , и . SoCC, стр. 143-147. IEEE, (2012)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , и 1 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , и . ICCAD, стр. 398-405. IEEE Computer Society, (2005)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 488-617. IEEE, (2007)