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A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.

, , , , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)

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Susumu Kuroda

Susumu Shikano

Susumu Iwabuchi

 

Другие публикации лиц с тем же именем

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , и . ICCAD, стр. 398-405. IEEE Computer Society, (2005)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications., , , , , , , , и . IEEE J. Solid State Circuits, 39 (4): 684-693 (2004)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 488-617. IEEE, (2007)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 326-606. IEEE, (2007)