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FVLLMONTI: The 3D Neural Network Compute Cube $(N^2C^2)$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation., , , , , , , , , и 25 other автор(ы). DATE, стр. 1-6. IEEE, (2024)1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors., , , и . ESSDERC, стр. 34-37. IEEE, (2017)InP DHBT test structure optimization towards 110 GHz characterization., , , , , , , и . ESSDERC, стр. 320-323. IEEE, (2022)First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design., , , , , , и . ESSDERC, стр. 150-153. IEEE, (2019)Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design., , , , , , , , , и . ESSDERC, стр. 57-60. IEEE, (2023)Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance., , , , , , , , , и 1 other автор(ы). BCICTS, стр. 1-7. IEEE, (2021)InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design., , , , , , , , и . BCICTS, стр. 1-4. IEEE, (2021)Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors., , , , , , , , , и 2 other автор(ы). VLSI-SoC, стр. 1-2. IEEE, (2022)3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model., , , , , , , , , и 1 other автор(ы). VLSI-SoC (Selected Papers), том 621 из IFIP Advances in Information and Communication Technology, стр. 301-321. Springer, (2020)0.4-μm InP/InGaAs DHBT with a 380-GHz $f_T$, > 600-GHz $f_\max$ and BVCE0 > 4.5 V., , , , , , , и . BCICTS, стр. 1-4. IEEE, (2021)