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Disambiguation of "Goel, Sandeep Kumar"

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Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

, , , , , , , , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)

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Sandeep Kumar

Sandeep Kumar

Sandeep Kumar Botla

Sandeep Kumar Parashar

Vishal Goel

 

Other publications of authors with the same name

Challenges and Solutions for 3D Fabric: A Foundry Perspective.. ISPD, page 93. ACM, (2022)Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)Innovative Practices Track: Test of 3D ICs & Chiplets., , and . VTS, page 1. IEEE, (2022)A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation., , , , , , , , and . ITC, page 11-20. IEEE, (2023)EDA solutions to new-defect detection in advanced process technologies., , , , , , and . DATE, page 123-128. IEEE, (2012)Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip., , , , and . DATE, page 108-113. IEEE Computer Society, (2004)Effective and Efficient Test Architecture Design for SOCs., and . ITC, page 529-538. IEEE Computer Society, (2002)Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study., , and . ITC, page 1-10. IEEE Computer Society, (2009)IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores., , , and . ITC, page 1203-1212. IEEE Computer Society, (2004)Cluster-Based Test Architecture Design for System-on-Chip., and . VTS, page 259-264. IEEE Computer Society, (2002)