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Disambiguation of "Chen, Ji-Jan"

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Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

, , , , , , , , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)

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Tzeng-Ji Chen

Chen Chen

Chen Chen

Hui Ji

Ji Vymer

 

Other publications of authors with the same name

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study., , , , , , , , , and 6 other author(s). ITC, page 1-10. IEEE Computer Society, (2013)DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement., , and . ATS, page 219-223. IEEE, (2007)Black-box leakage power modeling for cell library and SRAM compiler., , , , and . DATE, page 637-642. IEEE, (2011)A built-in self-test scheme for the post-bond test of TSVs in 3D ICs., , , , , and . VTS, page 20-25. IEEE Computer Society, (2011)An embedded wide-range and high-resolution CLOCK jitter measurement circuit., , , and . DATE, page 1637-1640. IEEE Computer Society, (2010)A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs., , , , , and . ITC, page 1-8. IEEE Computer Society, (2006)Diagnosis and Layout Aware (DLA) scan chain stitching., , , , , , , , , and 5 other author(s). ITC, page 1-10. IEEE Computer Society, (2013)Diagnosis for MRAM write disturbance fault., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2007)A Test Integration Methodology for 3D Integrated Circuits., , , , , and . Asian Test Symposium, page 377-382. IEEE Computer Society, (2010)