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Disambiguation of "Ishihara, Tohru"

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Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization.

, , and . SoCC, page 112-117. IEEE, (2018)

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Tohru Iwai

Aeka Ishihara

Hirofumi Ishihara

 

Other publications of authors with the same name

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization., , and . SoCC, page 112-117. IEEE, (2018)An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits., , and . DATE, page 1-2. IEEE, (2023)Value-dependence of SRAM leakage in deca-nanometer technologies., and . IEICE Electron. Express, 5 (1): 23-28 (2008)Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories., , and . ESTIMedia, page 13-18. IEEE Computer Society, (2007)A Power Minimization Technique for Arithmetic Circuits by Cell Selection., , , and . ASP-DAC/VLSI Design, page 268-273. IEEE Computer Society, (2002)A Standard Cell Optimization Method for Near-Threshold Voltage Operations., , , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 32-41. Springer, (2012)Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure., , , and . PATMOS, page 237-242. IEEE, (2018)An energy-efficient on-chip memory structure for variability-aware near-threshold operation., , and . ISQED, page 23-28. IEEE, (2015)An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers., , and . ASP-DAC, page 568-573. IEEE, (2022)Microarchitectural-level statistical timing models for near-threshold circuit design., , and . ASP-DAC, page 87-93. IEEE, (2015)