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NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.

, , and . DAC, page 711-716. ACM, (2006)

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Design space exploration of FinFET cache., and . JETC, 9 (3): 20:1-20:16 (2013)NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture., , and . DAC, page 711-716. ACM, (2006)User-perceived latency driven voltage scaling for interactive applications., , and . DAC, page 624-627. ACM, (2005)Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring., and . EURO-DAC, page 350-354. IEEE Computer Society, (1990)Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle., , and . ACM J. Emerg. Technol. Comput. Syst., 13 (4): 51:1-51:14 (2017)High-level energy macromodeling of embedded software., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1037-1050 (2002)Register binding-based RTL power management for control-flow intensive designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (8): 1175-1183 (2004)Fast Design Space Exploration of Nonlinear Systems: Part I., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 2970-2983 (2022)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1589-1602 (2006)Generation of distributed logic-memory architectures through high-level synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1694-1711 (2005)