Author of the publication

Fast Design Space Exploration of Nonlinear Systems: Part I.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 2970-2983 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design space exploration of FinFET cache., and . JETC, 9 (3): 20:1-20:16 (2013)NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture., , and . DAC, page 711-716. ACM, (2006)Analyzing the energy consumption of security protocols., , , and . ISLPED, page 30-35. ACM, (2003)User-perceived latency driven voltage scaling for interactive applications., , and . DAC, page 624-627. ACM, (2005)Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring., and . EURO-DAC, page 350-354. IEEE Computer Society, (1990)Fully Dynamic Inference with Deep Neural Networks., , , and . CoRR, (2020)Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs., and . IEEE Trans. Parallel Distributed Syst., 4 (8): 864-874 (1993)Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle., , and . ACM J. Emerg. Technol. Comput. Syst., 13 (4): 51:1-51:14 (2017)Register binding-based RTL power management for control-flow intensive designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (8): 1175-1183 (2004)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1589-1602 (2006)