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Disambiguation of "Vandersmissen, Kevin"

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Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm.

, , , , , , , , , , , , , , , , , , , , , , , and . VLSI Technology and Circuits, page 292-293. IEEE, (2022)

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Alexander Ali Kevin

Otto Bernd Vandersmissen

Kevin Niwek

Kevin Niwek

Kevin Thurley

 

Other publications of authors with the same name

Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Integration of a Stacked Contact MOL for Monolithic CFET., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning., , , , , , , , , and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 330-331. IEEE, (2022)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias., , , , , , and . 3DIC, page 1-4. IEEE, (2014)Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 292-293. IEEE, (2022)Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control., , , , , , , , , and 10 other author(s). ICICDT, page 88. IEEE, (2022)