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Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.

A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, B. Nguyen, I. Radu, E. Litta, and N. Horiguchi. VLSI Technology and Circuits, page 330-331. IEEE, (2022)

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Jacopo Grazzini

Jacopo Janner

Jacopo Negroni

Jacopo Mauro

Jacopo Ghiglieri

Other publications of authors with the same name

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.J. Franco, B. Kaczer, J. Mitard, M. Toledano-Luque, F. Crupi, G. Eneman, P. Rousse, T. Grasser, M. Cho, T. Kauerauf and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Hoffmann. ISCAS, page 2249-2252. IEEE, (2011)BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic.J. Franco, S. Graziano, B. Kaczer, F. Crupi, L. Ragnarsson, T. Grasser, and G. Groeseneken. Microelectron. Reliab., 52 (9-10): 1932-1935 (2012)Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, and G. Groeseneken. IEEE Trans. Circuits Syst. II Express Briefs, 59-II (7): 439-442 (2012)The properties, effect and extraction of localized defect profiles from degraded FET characteristics.M. Vandemaele, B. Kaczer, S. Tyaginov, J. Franco, R. Degraeve, A. Chasin, Z. Wu, E. Bury, Y. Xiang, H. Mertens and 1 other author(s). IRPS, page 1-7. IEEE, (2021)A BSIM-Based Predictive Hot-Carrier Aging Compact Model.Y. Xiang, S. Tyaginov, M. Vandemaele, Z. Wu, J. Franco, E. Bury, B. Truijen, B. Parvais, D. Linten, and B. Kaczer. IRPS, page 1-9. IEEE, (2021)Degradation mechanisms and lifetime assessment of Ge Vertical PIN photodetectors.K. Croes, V. Simons, B. Truijen, P. Roussel, K. Sever, A. Tsiara, J. Franco, and P. Absil. OFC, page 1-3. IEEE, (2022)Beyond-Si materials and devices for more Moore and more than Moore applications.N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, T. Ivanov, D. Lin, J. Mitard, S. Ramesh and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)A drift-diffusion-based analytic description of the energy distribution function for hot-carrier degradation in decananometer nMOSFETs.P. Sharma, S. Tyaginov, S. Rauch, J. Franco, B. Kaczer, A. Makarov, M. Vexler, and T. Grasser. ESSDERC, page 428-431. IEEE, (2016)Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.Z. Wu, J. Franco, D. Claes, G. Rzepa, P. Roussel, N. Collaert, G. Groeseneken, D. Linten, T. Grasser, and B. Kaczer. IRPS, page 1-7. IEEE, (2019)

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Disambiguation of "Franco, Jacopo"