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Disambiguation of "Huang, Shi-Yu"

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Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (8): 1258-1268 (2014)

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Yu Shi

Shi-Ming Huang

Yu-E Shi

Yu-Hwa Huang

Yu-Han Huang

 

Other publications of authors with the same name

Online slack-time binning for IO-registered die-to-die interconnects., , , , , and . ITC, page 1-8. IEEE, (2016)A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques., , and . ACM Trans. Design Autom. Electr. Syst., 13 (1): 9:1-9:27 (2008)A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL., and . ISOCC, page 90-91. IEEE, (2018)Small delay testing for TSVs in 3-D ICs., , , , , , and . DAC, page 1031-1036. ACM, (2012)Robust paradigm for diagnosing hold-time faults in scan chains., , and . IET Comput. Digit. Tech., 1 (6): 706-715 (2007)Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM., , and . IEEE J. Solid State Circuits, 44 (10): 2817-2823 (2009)Oscillation-Based Prebond TSV Test., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (9): 1440-1444 (2013)Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (5): 737-747 (2013)Circuit and Methodology for Testing Small Delay Faults in the Clock Network., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (10): 2087-2097 (2018)Pulse-Vanishing Test for Interposers Wires in 2.5-D IC., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (8): 1258-1268 (2014)