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Disambiguation of "Morf, Thomas"

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A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects.

, , , , , , , , and . IEEE J. Solid State Circuits, 40 (12): 2667-2679 (2005)

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Gregor Morfill

Geert Morf

Ulrich Morf

Heinrich Morf

Jan Morf

 

Other publications of authors with the same name

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology., , , , , , , and . ESSCIRC, page 67-70. IEEE, (2021)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)Designing (Not Only) Lunar Space Data Centers., , , , , , , , , and 2 other author(s). IGARSS, page 6104-6108. IEEE, (2024)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects., , , , , , , , and . IEEE J. Solid State Circuits, 40 (12): 2667-2679 (2005)22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)