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Disambiguation of "Lo, Yun-Chen"

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Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture.

, and . DAC, page 1-6. IEEE, (2023)

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Yun Chen

Yun Chen

Yun Chen

Yun Chen

Yun Chen

 

Other publications of authors with the same name

Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference., and . DAC, page 1-6. IEEE, (2023)Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture., and . DAC, page 1-6. IEEE, (2023)Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference., , and . ICLR, OpenReview.net, (2023)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices., , , , , , , , , and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators., , , , , , , , and . ICCD, page 515-522. IEEE, (2023)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips., , , , and . ASP-DAC, page 79-84. ACM, (2021)Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs., and . MICRO, page 1002-1015. ACM, (2023)Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)., , , , , , , and . ESSCIRC, page 241-244. IEEE, (2019)DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)