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Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.

C. Wang, Y. Lo, J. Wu, Y. Tsai, C. Chang, T. Hsu, M. Chu, C. Lai, and R. Liu. ICCD, page 515-522. IEEE, (2023)

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Shuo Liu

Shuo Li

Shuo Wang

Shuo Bai

Shuo Zhang

Other publications of authors with the same name

DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives.J. Huang, and R. Liu. ASP-DAC, page 34-39. IEEE, (2018)Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage.Y. Kuo, R. Chiu, and R. Liu. MSST, page 141-147. IEEE, (2019)DuraCache: a durable SSD cache using MLC NAND flash.R. Liu, C. Yang, C. Li, and G. Chen. DAC, page 166:1-166:6. ACM, (2013)Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems.W. Wu, C. Yeh, A. White, C. Wang, Z. Yeh, C. Hsieh, R. Liu, K. Tang, and C. Lo. AICAS, page 1-4. IEEE, (2021)A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model.H. Wu, W. Kao, H. Ku, C. Wang, C. Hsieh, R. Liu, K. Tang, and C. Lo. AICAS, page 1-4. IEEE, (2021)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips.P. Wu, J. Su, L. Hong, J. Ren, C. Chien, H. Chen, C. Ke, H. Hsiao, S. Li, S. Sheu and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)NVM duet: unified working memory and persistent store architecture.R. Liu, D. Shen, C. Yang, S. Yu, and C. Wang. ASPLOS, page 455-470. ACM, (2014)ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.Y. Lo, C. Yeh, J. Wu, C. Wang, Y. Tsai, W. Ting, and R. Liu. ICCAD, page 86:1-86:9. ACM, (2022)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices.P. Wu, J. Su, L. Hong, J. Ren, C. Chien, H. Chen, C. Ke, H. Hsiao, S. Li, S. Sheu and 7 other author(s). ISSCC, page 126-127. IEEE, (2023)

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Disambiguation of "Liu, Ren-Shuo"

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Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.

Please choose a person to relate this publication to

Shuo Liu

Shuo Li

Shuo Wang

Shuo Bai

Shuo Zhang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Ren-Shuo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.

Please choose a person to relate this publication to

Shuo Liu

Shuo Li

Shuo Wang

Shuo Bai

Shuo Zhang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.