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Disambiguation of "Pravossoudovitch, Serge"

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Power Driven Chaining of Flip-Flops in Scan Architectures.

, , , and . ITC, page 796-803. IEEE Computer Society, (2002)

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Elena Sergeyev

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Other publications of authors with the same name

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Intra-Cell Defects Diagnosis., , , , , , and . J. Electron. Test., 30 (5): 541-555 (2014)On hardware generation of random single input change test sequences., , , , and . ETW, page 117-123. IEEE Computer Society, (2001)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , and . J. Electron. Test., 24 (4): 353-364 (2008)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies., , , , and . DAC, page 857-862. ACM, (2005)A new test pattern generation method for delay fault testing., , , , and . VTS, page 296-301. IEEE Computer Society, (1996)