( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Efficient Hardware Acceleration of Convolutional Neural Networks.

, , , и . SoCC, стр. 191-192. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Kazimierz S kala

Helmut Kala

Helmut Kala

Helmut Kala

Helmut Kala

 

Другие публикации лиц с тем же именем

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit., , , , и . ISCAS, стр. 3034-3037. IEEE, (2013)Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme., , , и . IET Comput. Digit. Tech., 13 (2): 78-86 (2019)Hardware Acceleration of SpMV Multiplier for Deep Learning., , и . VDAT, стр. 1-6. IEEE, (2021)Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA., , и . APCCAS, стр. 65-69. IEEE, (2023)Approximate CNN on FPGA Using Toom-Cook Multiplier., , , и . iSES, стр. 271-276. IEEE, (2023)Adiabatic Physical Unclonable Function Using Cross-Coupled Pair., , , и . iSES, стр. 278-282. IEEE, (2022)UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs., , , и . VLSID, стр. 209-214. IEEE, (2019)A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform., , , и . VDAT, том 892 из Communications in Computer and Information Science, стр. 28-36. Springer, (2018)Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA., , , и . ISED, стр. 21-25. IEEE, (2018)Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems., , , и . ISED, стр. 20-24. IEEE Computer Society, (2014)