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Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , и . DATE, стр. 298-301. IEEE, (2020)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , и . DATE, стр. 1634-1639. IEEE, (2018)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , и 10 other автор(ы). DATE, стр. 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , и . DATE, стр. 1-6. IEEE, (2021)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , и . NANOARCH, стр. 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?, , , , и . LASCAS, стр. 1-4. IEEE, (2017)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , и 9 other автор(ы). IMW, стр. 1-4. IEEE, (2023)Technology variability from a design perspective., , , , , и . CICC, стр. 1-8. IEEE, (2010)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch., , , , и . ISCAS, стр. 3170-3173. IEEE, (2009)Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology., , , , и . ICICDT, стр. 53-56. IEEE, (2013)