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Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.

R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, E. Bourde-Cicé, M. Bellet, D. Turgis, and E. Beigné. NANOARCH, page 131-137. ACM, (2018)

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Alexander David

Wahyudi David

Florian Bodo David

Joachim David

Jürgen Davids

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Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.G. Moritz, B. Giraud, J. Noel, D. Turgis, and A. Grover. ICICDT, page 53-56. IEEE, (2013)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.R. Wilson, E. Beigné, P. Flatresse, A. Valentian, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.A. Feki, B. Allard, D. Turgis, J. Lafont, and L. Ciampolini. ISOCC, page 470-474. IEEE, (2012)Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.A. Grover, P. Kumar, M. Daud, G. Visweswaran, C. Parthasarathy, J. Noel, D. Turgis, B. Giraud, and G. Moritz. ICICDT, page 1-4. IEEE, (2015)Improving Ge-rich GST ePCM reliability through BEOL engineering.A. Redaelli, A. Gandolfo, G. Samanni, E. Gomiero, E. Petroni, L. Scotti, A. Lippiello, P. Mattavelli, J. Jasse, D. Codegoni and 27 other author(s). ESSDERC, page 231-234. IEEE, (2021)28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.K. Akyel, L. Ciampolini, O. Thomas, D. Turgis, and G. Ghibaudo. ESSDERC, page 94-97. IEEE, (2014)Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells.L. Ciampolini, J. Lafont, F. Drissi, J. Morin, D. Turgis, X. Jonsson, C. Desclèves, and J. Nguyen. ICCAD, page 89. ACM, (2016)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, E. Bourde-Cicé, M. Bellet, D. Turgis, and E. Beigné. NANOARCH, page 131-137. ACM, (2018)RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.J. Nguyen, D. Turgis, D. Bonciani, B. Lhomme, Y. Carminati, O. Callen, G. Guirleo, L. Ciampolini, and G. Ghibaudo. NATW, page 28-33. IEEE, (2016)

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Disambiguation of "Turgis, David"

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Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.

Please choose a person to relate this publication to

Alexander David

Wahyudi David

Florian Bodo David

Joachim David

Jürgen Davids

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Turgis, David"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.

Please choose a person to relate this publication to

Alexander David

Wahyudi David

Florian Bodo David

Joachim David

Jürgen Davids

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.