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Disambiguation of "Kajihara, Seiji"

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Innovative Test Practices in Asia.

, , , , , , , , , , , , and . VTS, page 1. IEEE, (2020)

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Seiji Miyashiro

Seiji Osawa

 

Other publications of authors with the same name

Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)A Statistical Quality Model for Delay Testing., , , , and . IEICE Trans. Electron., 89-C (3): 349-355 (2006)Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis., , , and . IEICE Trans. Inf. Syst., 78-D (7): 811-816 (1995)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout., , , , and . ITC, page 83-89. IEEE Computer Society, (2002)On validating data hold times for flip-flops in sequential circuits., , , , , and . ITC, page 317-325. IEEE Computer Society, (2000)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits., , and . Asian Test Symposium, page 147-152. IEEE Computer Society, (1999)An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification., , and . Asian Test Symposium, page 58-63. IEEE Computer Society, (1998)