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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.

J. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen, C. Augustine, J. Tschanz, and V. De. ISSCC, page 1-3. IEEE, (2015)

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Marcel Tschanz

Karl Tschanz

Michael James

Audrein James

Katherine James

Other publications of authors with the same name

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.S. Paul, V. Honkote, R. Kim, T. Majumder, P. Aseron, V. Grossnickle, R. Sankman, D. Mallik, S. Jain, S. Vangal and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar. DAC, page 486-491. ACM, (2002)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.S. Kim, Y. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)SUB 45nm Low Power Design Challenges.J. Tschanz. ISQED, page 4. IEEE Computer Society, (2007)Circuit techniques for dynamic variation tolerance.K. Bowman, J. Tschanz, C. Wilkerson, S. Lu, T. Karnik, V. De, and S. Borkar. DAC, page 4-7. ACM, (2009)A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.M. Khellah, M. Ghoneima, J. Tschanz, Y. Ye, N. Kurd, J. Barkatullah, S. Nimmagadda, and Y. Ismail. ICCD, page 253-257. IEEE Computer Society, (2005)14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS.S. Kim, H. Krishnamurthy, Z. Ahmed, N. Desai, S. Weng, A. Augustine, H. Do, J. Yu, P. Bach, X. Liu and 4 other author(s). ISSCC, page 270-272. IEEE, (2024)Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing.N. Desai, H. Krishnamurthy, K. Ahmed, S. Weng, S. Kim, X. Liu, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz and 1 other author(s). ISSCC, page 262-264. IEEE, (2021)Resilient microprocessor design for high performance & energy efficiency.K. Bowman, J. Tschanz, S. Lu, P. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik and 1 other author(s). ISLPED, page 355-356. ACM, (2010)

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Disambiguation of "Tschanz, James W."