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Disambiguation of "Mao, Zhigang"

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Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)

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Zhigang Shen

Zhigang Zhang

Zhigang Zhang

Zhigang Gao

Zhigang Zhang

 

Other publications of authors with the same name

Implementation of Java Card Virtual Machine., , and . J. Comput. Sci. Technol., 15 (6): 591-596 (2000)An efficient VLSI architecture for extended variable block sizes motion estimation., , and . SoCC, page 347-350. IEEE, (2010)Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding., , , and . IEICE Electron. Express, 13 (6): 20160019 (2016)A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator., , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (2): 25:1-25:22 (2019)A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis., , and . ICECS, page 766-769. IEEE, (2008)Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling., , , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2201-2219 (2020)Pareto based Multi-objective Mapping IP Cores onto NoC Architectures., , and . APCCAS, page 331-334. IEEE, (2006)Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit., , , , and . ASICON, page 1-4. IEEE, (2019)