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ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap.

, , , , and . ICCD, page 139-146. IEEE Computer Society, (2014)

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Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes., and . ISPD, page 83-90. ACM, (2021)Generative self-supervised learning for gate sizing: invited., , , , , and . DAC, page 1331-1334. ACM, (2022)BufFormer: A Generative ML Framework for Scalable Buffering., , , , and . ASP-DAC, page 264-270. ACM, (2023)Optimal Scheduling and Allocation for IC Design Management and Cost Reduction., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 22 (4): 60:1-60:30 (2017)Methodology for electromigration signoff in the presence of adaptive voltage scaling., , and . SLIP, page 6:1-6:7. IEEE Computer Society, (2014)High-dimensional metamodeling for prediction of clock tree synthesis outcomes., , and . SLIP, page 1-7. IEEE Computer Society, (2013)Toward Metrics of Design Automation Research Impact., , , , , and . ICCAD, page 263-270. IEEE, (2015)A deep learning methodology to proliferate golden signoff timing., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Learning-based prediction of embedded memory timing failures during initial floorplan design., , , , and . ASP-DAC, page 178-185. IEEE, (2016)Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper)., , , , and . ICCAD, page 1:1-1:8. ACM, (2022)