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Implicitly Parallel Programming Models for Thousand-Core Microprocessors., , , , , , , , , and 4 other author(s). DAC, page 754-759. IEEE, (2007)Rigel: A 1, 024-Core Single-Chip Accelerator Architecture., , , , , and . IEEE Micro, 31 (4): 30-41 (2011)Cohesion: An Adaptive Hybrid Memory Model for Accelerators., , , , and . IEEE Micro, 31 (1): 42-55 (2011)Rigel: an architecture and scalable programming interface for a 1000-core accelerator., , , , , , , , and . ISCA, page 140-151. ACM, (2009)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , and . IEEE Micro, 30 (1): 29-39 (2010)Hybrid coherence for scalable multicore architectures. University of Illinois Urbana-Champaign, USA, (2010)HybridOS: runtime support for reconfigurable accelerators., and . FPGA, page 212-221. ACM, (2008)Emµcode: Masking hard faults in complex functional units., , and . DSN, page 458-467. IEEE Computer Society, (2009)CUBA: an architecture for efficient CPU/co-processor data communication., , , , , and . ICS, page 299-308. ACM, (2008)Cohesion: a hybrid memory model for accelerators., , , , and . ISCA, page 429-440. ACM, (2010)