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Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.

, , , , , , and . IEEE J. Solid State Circuits, 41 (7): 1654-1661 (2006)

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A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 42 (1): 134-144 (2007)Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 392-401. Springer, (2004)Dynamic state-retention flip flop for fine-grained sleep-transistor scheme., , , , , , , , , and 2 other author(s). ESSCIRC, page 145-148. IEEE, (2005)A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion., , , , , and . IEEE J. Solid State Circuits, 43 (7): 1666-1676 (2008)A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions., , , , , , , , , and 9 other author(s). ISSCC, page 952-961. IEEE, (2006)Impact of process parameter variations on the energy dissipation in adiabatic logic., , , , , and . ECCTD, page 429-432. IEEE, (2005)Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits., , , , and . Conf. Computing Frontiers, page 414-420. ACM, (2005)Digitalization of mixed-signal functionality in nanometer technologies.. ICCAD, page 252-255. IEEE, (2010)Adaptive circuit block model for power supply noise analysis of low power system-on-chip., , , , , and . SoC, page 13-18. IEEE, (2009)Variation tolerant high resolution and low latency time-to-digital converter., , , , , and . ESSCIRC, page 194-197. IEEE, (2007)