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Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.

, , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 392-401. Springer, (2004)

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Jörg Berthold

Jörg Berthold

Jörg Berthold

Dorothea Jörg

Rainer Georg Jörgensen

 

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Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , и . DATE, стр. 792-793. IEEE Computer Society, (2010)A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions., , , , , , , , , и 9 other автор(ы). ISSCC, стр. 952-961. IEEE, (2006)Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes., , , , и . VLSI-SOC, стр. 246-251. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits., , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 789-798. Springer, (2004)Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes., , , , , и . VLSI-SoC (Selected Papers), том 200 из IFIP, стр. 229-245. Springer, (2003)Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead., , , , , , и . IEEE J. Solid State Circuits, 41 (7): 1654-1661 (2006)An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment., , , , , , и . ESSCIRC, стр. 599-602. IEEE, (2003)The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits., , , и . ISLPED, стр. 237-242. IEEE, (1996)Architecture and implementation of a Software-Defined Radio baseband processor., , , , , , , , , и 8 other автор(ы). ISCAS, стр. 2193-2196. IEEE, (2011)Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement., , , , , , и . ESSCIRC, стр. 308-311. IEEE, (2007)