Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , and . FTCS, page 263-270. IEEE Computer Society, (1992)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Design of High-Level Test Language for Digital LSI., , and . ITC, page 508-513. IEEE Computer Society, (1983)Cascade Realization of 3-Input 3-Output Conservative Logic Circuits., and . IEEE Trans. Computers, 27 (3): 214-221 (1978)A BIST Circuit for IDDQ Tests., , , , , and . Asian Test Symposium, page 390-395. IEEE Computer Society, (2003)Memory reduction of IDDQ test compaction for internal and external bridging faults., and . Asian Test Symposium, page 350-355. IEEE Computer Society, (2000)A high-speed IDDQ sensor implementation., , , and . Asian Test Symposium, page 356-361. IEEE Computer Society, (2000)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits., , and . Asian Test Symposium, page 121-126. IEEE Computer Society, (1999)IDDQ Current Dependency on Test Vectors and Bridging Resistance., , and . Asian Test Symposium, page 158-163. IEEE Computer Society, (1999)