Author of the publication

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.

, , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1735-1739 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link., , , , , and . VLSI Technology and Circuits, page 30-31. IEEE, (2022)A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop., , , , , , , , and . VLSI Circuits, page 94-. IEEE, (2019)6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels., , , , and . ISSCC, page 128-130. IEEE, (2020)29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration., , , , , , , and . ISSCC, page 494-495. IEEE, (2017)22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface., , , , and . ISSCC, page 340-342. IEEE, (2020)A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration., , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2525-2538 (2021)A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1735-1739 (2020)