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Disambiguation of "Cho, Sung-Yong"

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A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.

, , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2525-2538 (2021)

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Sung-Yong Cho

Sung-Jun Cho

Sung-bok Cho

Gyu-Sung Cho

Sung-Hyun Cho

 

Other publications of authors with the same name

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line., , , , , and . ESSCIRC, page 447-450. IEEE, (2014)A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration., , , , , , , and . ISSCC, page 494-495. IEEE, (2017)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH., , , , , , , , , and . VLSIC, page 136-137. IEEE, (2012)A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS., , , , and . A-SSCC, page 1-4. IEEE, (2015)256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration., , , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2525-2538 (2021)A new micro biological cell injection system., and . IROS, page 1642-1647. IEEE, (2004)