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Disambiguation of "Kumar, Raghavan"

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A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.

, , , , , , , , , , , and . VLSI Circuits, page 234-. IEEE, (2019)

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Raghavan Vallur

Sarada Raghavan

Raghavan Chinnadurai

Rohini Kumar

Pardeep Kumar

 

Other publications of authors with the same name

Side-Channel Assisted Modeling Attacks on Feed-Forward Arbiter PUFs Using Silicon Data., and . RFIDSec, volume 9440 of Lecture Notes in Computer Science, page 53-67. Springer, (2015)A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS., , , , , and . ISSCC, page 244-245. IEEE, (2023)Hybrid modeling attacks on current-based PUFs., and . ICCD, page 493-496. IEEE Computer Society, (2014)On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators., , and . ISVLSI, page 165-170. IEEE Computer Society, (2012)On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors., , and . ISVLSI, page 120-125. IEEE Computer Society, (2012)On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions., , and . VLSID, page 381-386. IEEE Computer Society, (2014)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits., , , , , , , and . ISSCC, page 308-310. IEEE, (2024)Program phase duration prediction and its application to fine-grain power management., , and . ISVLSI, page 127-132. IEEE Computer Socity, (2013)