( en | de | ru )

 

Disambiguation of "Anders, Mark A."

Author of the publication

copydeleteadd this publication to your clipboard
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.

, , , , , , , , , , , and . VLSI Circuits, page 234-. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mark A Nusselein

Mark A Awabdy

Mark A Nusselein

Mark Yampolsky

Maßnahmen zur Sicherung von E2E-QoS bei verketteten Diensten. Uni München, (2009)

Mark Schütte

Crf2 - ein neues Antigen von Aspergillus fumigatus. TU Braunschweig, (2009)
 

Other publications of authors with the same name

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS., , , , , , , , and . ESSCIRC, page 198-201. IEEE, (2010)Bias temperature instabilities in 4H SiC metal oxide semiconductor field effect transistors: Insight provided by electrically detected magnetic resonance., , , and . Microelectron. Reliab., (2018)A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core., , , , , , , , and . ISSCC, page 353-365. IEEE, (2006)A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS., , , , , , , , , and . A-SSCC, page 137-140. IEEE, (2019)A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS., , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)High-performance energy-efficient NoC fabrics: Evolution and future challenges.. NOCS, page i. IEEE, (2014)A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS., , , , , , and . ISSCC, page 316-317. IEEE, (2008)A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS., , , , , , , and . ISSCC, page 110-111. IEEE, (2010)A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS., , , , , , , and . ISSCC, page 184-186. IEEE, (2012)A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS., , , , , , and . ISSCC, page 178-180. IEEE, (2012)