( en | de | ru )

 

Disambiguation of "Kumar, Vinay B. Y."

Author of the publication

copydeleteadd this publication to your clipboard
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.

, , , and . VLSI-DAT, page 1-4. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vinay Kumar

Vinay Kumar Aggarwal

Vinay Suryaprakash

Vinay Bettadapura

Vinay Vijayakumar

 

Other publications of authors with the same name

Recruiting Fault Tolerance Techniques for Microprocessor Security., , , , , and . ATS, page 80-85. IEEE, (2019)A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis., , , , , and . ACISP, volume 12248 of Lecture Notes in Computer Science, page 525-542. Springer, (2020)Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks., , , , and . DATE, page 561-564. IEEE, (2021)FPGA-based implementation of M4RM for matrix multiplication over GF(2)., , and . VDAT, page 1-2. IEEE, (2014)Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems., , , and . VLSI-DAT, page 1-4. IEEE, (2014)Lightweight Forth Programmable NoCs., , , and . VLSID, page 368-373. IEEE Computer Society, (2018)Relaxation Based Circuit Simulation Acceleration over CPU-FPGA., , , , , and . VLSID, page 409-414. IEEE Computer Society, (2016)Parallel two step random walk algorithm to analyze VLSI power grid networks., , , , and . VDAT, page 1-2. IEEE Computer Society, (2015)Secure Your SoC: Building System-an-Chip Designs for Security., , , , , , and . SoCC, page 248-253. IEEE, (2020)