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Low Power Combinational Multipliers using Data-driven Signal Gating.

, and . APCCAS, page 1430-1433. IEEE, (2006)

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High Level Synthesis of Degradable ASICs Using Virtual Binding., , , , and . VTS, page 311-317. IEEE Computer Society, (2007)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)APDL: A Processor Description Language For Design Space Exploration of Embedded Processors., , , and . FDL, page 50-55. ECSI, (2007)Record-Replay Architecture as a General Security Framework., , , , and . HPCA, page 180-193. IEEE Computer Society, (2018)DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism., , , , , , , , and . PACT, page 155-166. IEEE Computer Society, (2011)Power efficient sequential multiplication using pre-computation., , , and . ISCAS, IEEE, (2006)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , and . ISCAS, page 1065-1068. IEEE, (2007)Record and deterministic replay of parallel programs on multiprocessors. University of Illinois Urbana-Champaign, USA, (2014)RelaxReplay: record and replay for relaxed-consistency multiprocessors., and . ASPLOS, page 223-238. ACM, (2014)Asymmetric Memory Fences: Optimizing Both Performance and Implementability., , and . ASPLOS, page 531-543. ACM, (2015)