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8T single-ended sub-threshold SRAM with cross-point data-aware write operation., , , , и . ISLPED, стр. 169-174. IEEE/ACM, (2011)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , и 9 other автор(ы). ISCAS, стр. 1468-1471. IEEE, (2013)Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor., , , , , , , , , и 1 other автор(ы). IBM J. Res. Dev., 41 (4&5): 489-504 (1997)Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation., , и . SoCC, стр. 105-109. IEEE, (2013)A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control., , , , , , , , , и 3 other автор(ы). SoCC, стр. 110-115. IEEE, (2013)A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry., , , и . ISCAS, стр. 381-384. IEEE, (2009)"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)., , , и . ISLPED, стр. 203-206. ACM, (2000)Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell., , , , и . ISLPED, стр. 255-258. ACM, (2014)Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells., , , и . ISCAS, стр. 601-604. IEEE, (2015)Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , и . ISCAS, стр. 2325-2328. IEEE, (2015)