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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang, T. Hsu, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. ISSCC, page 494-496. IEEE, (2018)

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Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

Other publications of authors with the same name

A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring.C. Yin, and C. Hsieh. VLSI-DAT, page 1-4. IEEE, (2013)A dual-mode CMOS image sensor for optical wireless communication.C. Lin, C. Hsieh, C. Lin, and R. Chen. VLSI-DAT, page 1-4. IEEE, (2014)An 8-bit column-shared SAR ADC for CMOS image sensor applications.J. Lin, K. Chang, C. Kao, S. Lo, Y. Chen, P. Lee, C. Chen, C. Yin, and C. Hsieh. ISCAS, page 301-304. IEEE, (2015)A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization.C. Kao, S. Hsieh, and C. Hsieh. A-SSCC, page 213-216. IEEE, (2017)A hybrid CMOS-imager with perovskites as photoactive layer.P. Yen, Y. Lin, S. Yu, S. Lou, K. Chuang, B. Chuang, A. Chiou, and C. Hsieh. IEEE SENSORS, page 1-3. IEEE, (2016)Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee.J. Keane, C. Hsieh, and B. Verbruggen. ISSCC, page 368-369. IEEE, (2021)A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.C. Xue, J. Hung, H. Kao, Y. Huang, S. Huang, F. Chang, P. Chen, T. Liu, C. Jhang, C. Su and 8 other author(s). ISSCC, page 245-247. IEEE, (2021)A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.Y. Chiu, W. Khwa, C. Li, F. Hsieh, Y. Chien, G. Lin, P. Chen, T. Pan, D. You, F. Chen and 8 other author(s). ISSCC, page 496-497. IEEE, (2023)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.C. Xue, T. Huang, J. Liu, T. Chang, H. Kao, J. Wang, T. Liu, S. Wei, S. Huang, W. Wei and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)A new CMOS image sensor readout structure for 3D integrated imagers.S. Yeh, J. Lin, C. Hsieh, K. Yeh, and C. Li. CICC, page 1-4. IEEE, (2011)

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Disambiguation of "Hsieh, Chih-Cheng"

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hsieh, Chih-Cheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.